As a standing study group, the PDMS-SSG will operate with an open-ended completion date. The PDMS-SSG will conduct a continuous long-term study of vital and high-impact issues relating to parallel and distributed modeling and simulation. A draft PDMS report will be co-developed and regularly updated by participants of the PDMS-SSG. It is anticipated that this report will impact M&S acquisition decision makers for future development.
Three critical areas of modern microprocessor chip design have hit the performance wall. These are listed below:

1. Increasing processor clock speeds beyond current capabilities results in excessive power consumption and/or heating.

2. Complex multi-level memory caching techniques that pre-fetch data are currently used to reduce memory access times and cannot be easily optimized further.

3. Pipeline processing, hyper-threading, branch prediction, and other instruction-level parallelism techniques are extensively used by current chip designs and cannot be easily optimized further.

Even if one or two of these performance walls could be improved, all three must advance together to achieve actual performance gains for typical software applications. The computing industry has come to the conclusion that the only feasible way forward is to exploit the use of multicore chips that provide multiple processors (or cores) within a single chip.